1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a single wafer having a plurality of integrated circuit chips having different chip sizes formed on the single wafer, for a high density packaging.
2. Description of Related Art
Japanese Patent Application Pre-examination Publication No. JP-A-04-373131 (the content of which is incorporated by reference in its entirety into this application and also an English abstract of JP-A-04-373131 is available from the Japanese Patent Office and the content of the English abstract of JP-A-04-373131 is also incorporated by reference in its entirety into this application) discloses two prior art IC (integrated circuit) chips, one of which is shown in FIG. 1, and the other of which is shown in FIG. 2. The IC chip 101 shown in FIG. 1 includes a plurality of external connection lands (simply called "lands" hereinafter) 102 located on only a periphery of the IC chip. The IC chip 201 shown in FIG. 2 includes a number of lands 202 located over the whole of the IC chip with a predetermined constant pitch to form a matrix of the lands.
In the type shown in FIG. 1, when a plurality of IC chips having different chip sizes are formed, the positional relation of each land from a center of the chip is different from one chip to another.
Therefore, when a plurality of IC chips having different chip sizes are formed on a single wafer, at the time of carrying out a function text under a wafer condition it is difficult to use a testing tool (for example, a probe card) in common to all the IC chips of the different chip sizes. The reason for this is that, since power supply voltage supplying positions are geometrically determined in the probe card, the power supply voltage supplying positions cannot be easily changed by modifying the setting of a signal processing apparatus connected to the probe card. Therefore, if the probe for supplying the power supply voltage is contacted to an adjacent different chip, a current flows in the adjacent chip, with the result that a proper test result can be no longer obtained.
On the other hand, since the geometrical location of the lands is normalized in the type shown in FIG. 2, when a plurality of IC chips having different chip sizes are formed, the positional relation of each land from a center of the chip is unified among the IC chips of the different chip sizes. Therefore, when it is intended to form a wafer having a plurality of IC chips having different chip sizes formed thereon, the type shown in FIG. 2 is excellent from the viewpoint that masks and probes can be used in common to the IC chips of the different chip sizes.
However, when the wafer is cut out into individual chips, if the pitch of the lands is small, it becomes difficult to form a dicing line, because a cutting margin for the dicing (for example, the thickness of a blade of the dicing saw plus a deviation margin, or a diameter of a laser beam in the case of a laser beam cutting) inevitably limits the interval of the lands. In particular, when a plurality of IC chips having different chip sizes are formed on a single wafer, since the dicing becomes more difficult than an ordinary case in that the IC chips of the same size are formed on a single wafer, a sufficient cutting margin is required.
Recently, the wafer used in manufacturing a semiconductor integrated circuits has become large, and has reached 12 inches in diameter in a mass production. In a logic circuit LSI (large scale integrated circuit), on the other hand, "many-kinds but small-production" has become spread. Therefore, in a logic LSI having only a small production amount required, when the logic LSIs of the number corresponding to one wafer were produced, the production becomes excessive, with the result that most of the LSI produced must be disposed.
In order to overcome this problem, if a plurality of kinds of chip having different chip sizes can be formed on a single wafer, a production having no waste becomes possible. In this case, however, a wasteful chip is not produced, but it becomes necessary to previously prepare a testing tool (for example, a probe card) fitted to each of the different chip sizes, in order to carry out the function test in a wafer condition, and also it becomes necessary to replace the testing tool from one kind of chip to another kind. As a result, the efficiency of production becomes low. Therefore, a countermeasure for overcoming this problem is now demanded.